One field in which a substrate or sample may have a surface topography that includes surface structure elements is the semiconductor field. For example, an array of grooves or trenches may be formed in the surface of a semiconductor substrate by etching to provide locations at which isolation material may be provided to isolate different device structures of the same substrate. As another possibility, an array of grooves or trenches may be etched into a substrate to define gate structures of for example a non-planar insulated gate field effect device or to define a recessed gate junction field effect device. Such an array of grooves or trenches may have, for example, an array pitch of a few micrometers, a sub-micron trench width, and a trench depth that lies in the range of 0.1 to 10 micrometers. As another possibility, device structures may be formed in walls or mesas provided on a surface. The properties of the resulting devices may be determined at least in part by the array pitch and the widths and depths/heights of such surface structure elements and it is desirable to be able to check that the surface structure elements once formed are of the width and depth required for the device specification.
One way of determining the width and height or depth of such surface structure elements is by cleaving a number of samples through a groove or trench to produce cross-section samples and then examining those cross-section samples using scanning electron microscopy (SEM). This is, however, inevitably a destructive testing process.